Integrated circuit technology has revolutionized various fields, including computers, control systems, telecommunications, and imaging. For example, in the imaging field, active pixel CMOS image sensors have proved to be less expensive to manufacture relative to CCD imaging devices. Further, for certain applications CMOS devices are superior in performance. The pixel elements in a MOS device can be made smaller and therefore provide a higher resolution than CCD image sensors. In addition, the signal processing logic necessary can be integrated alongside the imaging circuitry, thus allowing for a single integrated chip to form a complete stand alone imaging device.
As noted in U.S. Pat. No. 5,625,210 to Lee et al. (“the '210 patent”), an active pixel sensor refers to an electronic image sensor with active devices, such as transistors, that are within each pixel. Conventional active pixel sensors typically employ photodiodes as the image sensing elements. The most popular active pixel sensor structure consists of three transistors and an N+/P-well photodiode, which is a structure that is compatible with the standard CMOS fabrication process. It is desirable for the active pixel to have high sensitivity, combined with a low dark current (i.e., the current that is output form the sensor in a dark environment). Excessive dark current lowers the dynamic range of the CMOS image sensor because there is insufficient ability to distinguish between light and dark conditions.
In the design of active pixel sensors, it is known that for the same sensor size, a deeper junction photodiode will have a higher sensitivity than that of a shallow junction (such as in a typical N+/P-well). However, the production of such devices usually requires modifications to the standard CMOS fabrication process, and in addition may increase dark current due to larger effective junction areas (when considered from a three-dimensional perspective).
Thus, two of the presently available alternatives are to either use the standard three-transistor plus N+/P-well photodiode structure that can be formed with the standard CMOS fabrication process, or else abandon the standard CMOS fabrication process in favor of designs that are intended to improve the sensitivity and dark current characteristics.
One active pixel sensor design that is not fabricated using the standard CMOS fabrication process is the pinned photodiode, as taught in the '210 patent. The pinned photodiode has gained favor for its ability to have good color response for blue light, as well as advantages in dark current density. Reduction in dark current is accomplished by pinning the diode surface potential to the P-well or P-substrate (GND) through a P+ region. An improvement to the '210 patent is shown in U.S. Pat. No. 5,880,495, assigned to the assignee of the present invention.
Nevertheless, the pinned photodiode configuration still has certain drawbacks. For example, in a pinned photodiode structure, there are four transistors, so the fill factor is smaller for the same area, which results in less sensitivity. In addition, the fabrication process for such a configuration requires significant modification form the standard CMOS fabrication prices, due to the buried channel transistor. The pinned photodiode configuration may cause image lag due to the incomplete transfer of charge from the diode to the floating node, if the junction profile is not perfectly optimized for the charge transfer.
Another approach compatible with standard CMOS processes is to use a hydrogen anneal process to reduce dark current by passivating dangling silicon bonds. For example, U.S. Pat. No. 6,271,054 discloses using such a method in the context of a CCD device. However, subsequent thermal processes inherent in CCD processes, due to the poor thermal stability of the silicon-hydrogen structure, may easily destroy the effect of hydrogen passivation.